CERN Computing Seminar

Parallel processing at low power - Field Programmable Gate Array of dreams?

by Bill Jenkins (Altera)

Europe/Zurich
31/S-028 (CERN)

31/S-028

CERN

30
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Description

Altera is one of the industry's Field Programmable Gate Array (FPGA) manufacturers with sales in 2014 of more than $1bn. 
The company has been investing considerable effort in a next generation of programming tools for FPGAs that should be able to take advantage of the devices' inherent ability for large-scale parallel processing.  Initial results look very promising with the company claiming up to 1.5 TFLOPS of DSP performance with significantly reduced power consumption compared to GPU solutions.

Their solution will be presented at CERN by Bill Jenkins, an Altera OpenCL expert.  Bill has an extensive technical background having started as a HW engineer doing board design for commercial and government applications before moving into system architecting and algorithm implementation/partitioning on CPUs, GPUs and FPGAs.

His expertise now also covers Altera's OpenCL and High Level Synthesis products. 

Please find more details of the presentation below.

Agenda: 

· FPGAs vs GPUs (at a higher level)
· Altera tool flow and the advantages of OpenCL with FPGAs
· Roadmap of tools and overview of the work we have done
· General Q&A session / discussion

 

 

Organised by

John Evans, IT Department