CERN Computing Seminar

Unlock performance secrets of next-gen Intel hardware

by Dr Zakhar A. Matveev (Intel Corp.)

Europe/Zurich
31/3-004 - IT Amphitheatre (CERN)

31/3-004 - IT Amphitheatre

CERN

105
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Description

Software must be optimized for both threaded and SIMD vector parallelism to achieve scaled performance on modern machines. The gap (often 2 orders of magnitude) between modernized workloads and unoptimized baselines is increasing with every next hardware generation.

SIMD code modernization is not without cost, but exciting new features of OpenMP 4.0 "explicit vectorization" and new Intel® "Vectorization Advisor" software tool make it possible to introduce efficient and portable SIMD parallelism without disrupting ongoing development.

In addition to vector parallelism topic, the seminar will cover adjacent "code modernization" areas like new types of memory available in Next Generation Intel® Xeon Phi Product.

About the speaker

Zakhar is a software architect in Intel SSG group. His current role is Parallel Studio architect with focus on SIMD vector parallelism assistance tools. Before it he was working as Intel Advisor XE software architect and software development team-lead. Before joining Intel he was focusing on complex broadcast / network automation systems usability, design and development. Zakhar received a PhD in computer graphics and performance optimization from NNGASU (2011). He received M.S. degree in mathematical modeling and computer science from Nizhny Novgorod state university (2005). His professional interests are in the areas of high performance optimization, parallel programming, software design and usability.


Organised by: Fons Rademakers and Miguel Angel Marquina
Computing Seminars /IT Department

more information
Slides
Video in CDS