CERN Computing Seminar

The rise of HPC accelerators: towards a common vision for a petascale future

by Filippo Spiga (ICHEC, Dublin)

Europe/Zurich
IT Auditorium (CERN)

IT Auditorium

CERN

Description

Nowadays new exciting scientific discoveries are mainly driven by large challenging simulations. An analysis of the trends in High Performance Computing clearly show that we hit several barriers (CPU frequency, power consumption, technological limits, limitations of the present paradigms) that we cannot easily overcome. In this context, accelerators became the concrete alternative to increase the compute capabilities of the deployed HPC clusters inside Universities and research centers across Europe. Within the EC funded "Partnership of Advanced Computing in Europe" (PRACE) project, several actions has been taken and will be taken to enable community codes to exploit accelerators in modern HPC architectures. In this talk, the vision and the strategy adopted by the PRACE project will be presented, focusing on new HPC programming model and paradigm. Accelerators are a fundamental piece to innovate in this direction, from both the hardware and the software point of view. This work started during the PRACE Preparatory Phase (2008-2010) and has been carried on during the PRACE First Implementation Phase (1IP, 2010-2012).

About ICHEC

The Irish Centre for High-end Computing (ICHEC) leads the Sub-Task "Accelerator" within the Task "Programming Techniques for High Performance Applications" inside the Work Package "Enabling Petascale Applications: Efficient use of Tier-0 systems". The main porting activities performed until now concern the adoption of GP-GPU technologies (mainly NVIDIA® CUDA) in real applications. ICHEC is directly involved in the porting of Quantum ESPRESSO and EC-EARTH/IFS, a material science and a weather forecast code. We expect in the Second Implementation Phase (2IP, 2011-2013) to explore and assess the adoption of OpenCL to target a wide portfolio of accelerators like ATI® GPU, AMD® APU or Intel® Many Integrated Core Architecture. Portability, reliability and maintenance of future codes will be fundamental aspects to evaluate and adopt new hardware.


Notice: This presentation contains personal opinions, forecasts and forward-looking statements of the authors and not necessarily the opinions of any other person or organization mentioned. For official communications and disclosures please refer to PRACE or ICHEC websites.


Organised by: Alfio Lazzaro and Miguel Angel Marquina
Computing Seminars /IT Department

Slides
Video in CDS